Despite the significant improvements in semiconductor device speeds over the last decade, the need for devices with improved performance characteristics persists. In particular, the introduction of more powerful software applications and operating systems has created a need for chips and other semiconductor devices that can perform a larger number of calculations in less time. Since the speed of semiconductor devices is governed in part by carrier transport properties, a great deal of attention has been focused in the art on methods for improving the carrier transport properties of semiconductor devices.
One method for improving the carrier transport properties of a semiconductor device is through the creation of a strained silicon channel layer in the device. Strain may be imparted to the channel layer by modifying its lattice structure. For example, if the channel layer is formed by depositing a layer of silicon over another material, such as SiGe, which has a comparatively larger lattice spacing, the silicon atoms in the channel layer will “stretch” to line up with the underlying Si and Ge atoms, thereby inducing strain in the channel layer. The presence of such strain has an advantageous effect on the transport properties of the channel layer. In particular, electrons and holes may experience less resistance, and hence greater mobility, in strained silicon as compared to unstrained silicon. Consequently, devices utilizing a well-defined strained silicon channel layer typically have higher drive than their unstrained counterparts.
One method known in the art for inducing channel strain in a semiconductor device is through the epitaxial growth of a strained layer in pre-recessed source/drain regions of the device. This may be accomplished by etching suitable trenches in the device, and then backfilling the trenches through epitaxial growth. The epitaxial layer is formed from a material which has a lattice constant which is different from the lattice constant of the substrate, thereby inducing strain in the device channel region, with the attendant improvement in carrier transport properties. Since it is desirable not to use a gate hard mask during this procedure, the gate region of the semiconductor device is exposed to the processing conditions attendant to source/drain etching and epitaxy. Unfortunately, at the conclusion of these processes, the profile of the gate electrode is often found to be distorted.
There is thus a need in the art for a method for making transistors with strained semiconductor channel layers that does not suffer from the aforementioned infirmity. In particular, there is a need in the art for a method for making semiconductor devices with strained channel layers through a source/drain epitaxial growth process that does not result in distortions in the profile of the gate electrode. There is further a need in the art for transistors made by such a process. These and other needs may be met by the devices and methodologies described herein.